In conventional processes for manufacturing a MOSFET device, the well depth required for achieving a desired channel length is dependent upon or dictated by lateral and vertical diffusion of dopant material beneath the edge of a polysilicon gate. Where the device being formed is intended to be a reduced depth or shallow well device, such a diffusion dependency tends to make the resulting device prone to short channel effects and high drain-source leakage. More particularly, in a conventional MOSFET process, respective steps of which for an N-channel or P-well device are shown in fragmentary, diagrammatic, sectional FIGS. 1-7, an N- epitaxial layer 11 is initially ubiquitously deposited upon an underlying N+ silicon substrate 13 (FIG. 1), to a prescribed thickness and resistivity for achieving a prescribed breakdown voltage.
Next, a gate insulator (oxide) layer 15 is grown on the top surface of the N- epitaxial layer 11 (FIG. 2), followed by non-selective deposition of a layer 19 of polycrystalline silicon (FIG. 3), which is to serve as the gate electrode for the device. The gate oxide 15 and polysilicon layer 19 are then selectively etched (FIG. 4) to define a self-aligned mask 21 for subsequent well and source implants.
As shown in FIG. 5, a P-well region 25 is then formed in the epitaxial layer 11 by means of a blanket or non-selective implant of P-type impurities 23, having an energy and concentration that produces the P-well region 25 adjacent to the side edge 27 of the gate mask 21. This structure is then subjected to a drive-in diffusion/anneal, which increases the depth of the P-well region 25 and causes lateral diffusion of the implanted P-well impurities beneath the gate mask 21, so that a resulting PN junction 27, between the P-well region 25 and the N- epitaxial layer 11, extends from the bottom 29 of the well P-region to a location 31 beneath the insulated gate structure.
Next, as shown in FIG. 6, an N+ source region 33 is selectively implanted into the well adjacent to the side edge 27 of the gate, using a separate photoresist mask and an oxide spacer or photoresist mask overlying the P-well region 25, to define the size of the source region. An area 50 directly below the gate oxide 15 and located between the N+ source region 33 and drain 11, 13 is now formed and defined as a channel area. Following formation of the N+source region 33, a further P+ implant is carried out, to Do form a surface P+ body region 35 within the P-well region (FIG. 7). The structure is then annealed for dopant activation and repair of damaged lattice sites. In the final device, the back side of the substrate will serve as a drain contact.
FIG. 8 diagrammatically illustrates the concentration of current flow during the on-state of a device manufactured using the conventional processing sequence of FIGS. 1-7. As pointed out above, because the length of the channel 50 is determined by lateral and vertical diffusion of dopant material beneath the side edge 27 of the gate structure, at the location of the well implant to form a relatively shallow well device (less than two microns in the illustrated example), the resulting device is prone to short channel effects and high drain-source leakage and in extreme cases breakdown voltage reduction.
The short channel effects are evident when the device is in conduction or on-state. In the on-state, charge carriers flow through the channel region between the source and drain regions under the control of the voltage applied to the gate electrode relative to the voltage applied to the source region. In the illustrated device having a P-type channel region 50 disposed between the N-type source region 33 and drain regions 11, 13 a positive voltage is applied to the gate electrode 19 for attracting electrons toward the surface of the channel region. The attracted electrons, when of sufficient concentration, invert the conductivity type of a narrow portion of the P-type channel region adjacent to the substrate surface to N-type for establishing a continuous path of N-type conductivity from the source region 33 through the channel region 50 to the drain region 11 and 13 down to the backside drain contact.
The applied gate-source voltage at which a significant current start to flow is called threshold voltage of the device. Normally for non-short channel devices this voltage is independent of gate length and width. As the channel length is reduced, the depletion layer of the source and drain junction become comparable to the channel length. At this point punch-through will occur. At punch-through, the two depletion layers merge and the gate can no longer control the current. The threshold voltage of the device is reduced and variable.
Threshold voltage control is the basic requirement for a MOSFET device. In the off-state or blocking state, the device is expected to support a desired drain-source voltage. Again, as the channel length is reduced, the depletion layers of the source and drain junctions become comparable to the channel length. At this point, punch-through will occur, so that the two depletion layers merge and the device can no longer support voltage. This premature breakdown voltage reduction due to short a channel greatly reduces the device's capability and usage.